Application Specific Integrated Circuits (ASICs) are designed to provide adequate performance for specific applications that could otherwise not be provided by a traditional processor and software. However, ASIC design costs and complexity increase exponentially with each new generation, while the products that use them drop in price at equally astonishing rates. Field Programmable Gate Arrays (FPGAs) offer many advantages compared to ASICs, including reduced non-recurring engineering costs, post-deployment reconfigurablity, and reduced time-to-market. The resulting circuit, however, will be slower, consume more power, and utilize significantly more silicon resources than its ASIC equivalent. These gaps are significant, but tolerable, for finite state machines and control-dominated applications, but become more pronounced for arithmetic-dominated applications such as video coding, Finite Impulse Response (FIR) filters, and 3G wireless base station channel cards.
To improve arithmetic performance, several researchers proposed carry chains that could efficiently embed circuitry that could perform fast addition inside a series of adjacent logic blocks. Commercial vendors have adopted carry chains in various heretofore known devices. For example, the Xilinx Virtex-4/5 CLBs available from Xilinx Inc. of San Jose, Calif., can send propagate/generate signals to adjacent blocks.
The Altera Stratix II/III/IV Adaptive Logic Modules (ALMs) implement ripple-carry addition. In the Stratix II ALM device, Altera Corporation of San Jose, Calif. introduced support for ternary, addition using the carry-chains. The Look-Up Tables (LUTs) act as carry-save adders (3:2 compressors), and the carry chain adds the result. This structure has been retained in the Stratix III and IV devices, which have followed.
Many other academic groups have also proposed carry chains for a variety of adder architectures. See, e.g., Cherepacha, D., and Lewis, D. DP-FPGA: an FPGA architecture optimized for datapaths, VLSI Design vol. 4, no. 4, 1996, 329-343; Frederick, M. T., and Somani, A. K. Multi-bit carry chains for high performance reconfigurable fabrics. International Conference on Field Programmable Logic and Applications (FPL '06) (Madrid, Spain, Aug. 28-30, 2006) 1-6; Hauck, S., Hosler, M. M., and Fry, T. W. High-performance carry chains for FPGAs, IEEE Transactions on VLSI Systems, vol. 8, 138-147; Kaviani, A., Vranisec, D., and Brown, S. Computational field programmable architecture. IEEE Custom Integrated Circuits Conference (CICC '98) (Santa Clara, Calif., USA, May 11-14, 1998) 261-264; and Leijten-Nowak, K., and Van Meerbergen, J. L. An FPGA architecture with enhanced datapath functionality. International Symposium on FPGA (FPGA '03) (Monterey, Calif., USA, Feb. 23-25, 2003) 195-204.
Hard intellectual property (IP) cores, e.g., digital signal processor/multiplier-accumulator (DSP/MAC) blocks, have heretofore been embedded into FPGAs. See Zuchowski, P. S., Reynolds, C. B., Grupp, R. J., Davis, S. G., Cremen, B., and Troxel, B. A hybrid ASIC and FPGA architecture, Int. Conf. Computer-Aided Design (ICCAD '02) (San Jose, Calif., USA, Nov. 10-14, 2002) 187-194. However, it has been recognized that the benefits of IP cores could be lost due to mismatches in bit-width. See, Kuon, I., and Rose, J. Measuring the gap between FPGAs and ASICs. IEEE Trans. Computer-Aided Design, vol. 26, no. 2, February, 2007, 203-215.